 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4019B MSI Quadruple 2-input multiplexer Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple 2-input multiplexer DESCRIPTION The HEF4019B provides four multiplexing circuits with common select inputs (SA, SB); each circuit contains two inputs (An, Bn) and one output (On). It may be used to select four bits of information from one of two sources. HEF4019B MSI The A inputs are selected when SA is HIGH, the B inputs when SB is HIGH. When SA and SB are HIGH, output (On) is the logical OR of the An and Bn inputs (On = An + Bn). When SA and SB are LOW, output (On) is LOW independent of the multiplexer inputs. Fig.1 Functional diagram. HEF4019BP(N): HEF4019BD(F): HEF4019BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING SA, SB A0 to A3 FAMILY DATA, IDD LIMITS category MSI See Family Specifications B0 to B3 O0 to O3 select inputs (active HIGH) multiplexer inputs multiplexer inputs multiplexer outputs Fig.2 Pinning diagram. January 1995 2 Philips Semiconductors Product specification Quadruple 2-input multiplexer HEF4019B MSI Fig.3 Logic diagram. TRUTH TABLE SELECT SA L H H L L H H H Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial SB L L L H H H H H INPUTS An X L H X X H X L Bn X X X L H X H L OUTPUT On L L H L H H H L January 1995 3 Philips Semiconductors Product specification Quadruple 2-input multiplexer AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays An, Bn, SA, SB On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL 70 30 25 60 25 15 60 30 20 60 30 20 145 60 50 130 50 35 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns 43 ns + 19 ns + 17 ns + 33 ns + 14 ns + 7 ns + 10 ns + 9 ns + 6 ns + 10 ns + 9 ns + 6 ns + SYMBOL TYP. MAX. HEF4019B MSI TYPICAL EXTRAPOLATION FORMULA (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (0,55 ns/pF) CL (0,23 ns/pF) CL (0,16 ns/pF) CL (1,0 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL (1,0 ns/pF) CL (0,42 ns/pF) CL (0,28 ns/pF) CL VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 1200 fi + (foCL) x VDD2 5100 fi + (foCL) x VDD2 18 700 fi + (foCL) x VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) APPLICATION INFORMATION An example of an application for the HEF4019B is: * True/complement selection. January 1995 4 |
Price & Availability of HEF4019B
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |